Dynamic Register Renaming Through Virtual-Physical Registers
Journal of Instruction Level Parallelism, 2000
In Summary
The authors propose a simple change to PRF allocation that aims to reduce register pressure from the normal conservative allocation strategy of allocating an entry at decode and freeing an entry at retirement of the next instruction to write the same logical register. The proposed change is to instead allocate a VP (Virtual-Physical) register at decode time, initially unassociated with a physical register, and allocating (from a smaller pool) a P (physical) register when the execute stage finishes. The newly-assigned P reg is associated with the instructions destination VP reg, and dependent ops (which would source the VP reg) will update their issue queue entries to show that the corresponding source reg is ready in the concomitant P reg.
The main added complexity comes from handling the potential deadlock case of an instruction reaching the end of execute (when PRFs are finally allocated) and finding that all PRF entries are currently allocated to program-newer instructions. The authors provide two possible remedies for this situation to avoid deadlock.
Takeaways
This paper does a good job at describing the register pressure on “conventional” PRF designs, and the proposed solutions (vp-NRR, which reserves registers for the NRR oldest instructions, and vp-DSY, which steals P regs from younger instructions to avoid deadlocks) seem straightforward to implement.
I need to do more reading on this, but from a (relative) lay perspective, this seems like a good starting point for reading about register renaming if you’re not already steeped in it. It’s recent enough to seem relevant, but does a good job of explaining the problem it’s trying to solve.
